(1) Technical Field
This invention relates to a method for planarizing an integrated circuit device, and more particularly, to a method of planarizing a submicron integrated circuit device by eliminating micro scratches after a chemical mechanical polishing process.
(2) Description of the Prior Art
The following four documents relate to methods dealing with semiconductor isolation for improving the isolation characteristics of semiconductor devices prior to planarizing by chemical mechanical polishing.
U.S. Pat. No. 5,728,621 issued Mar. 17, 1998 to Zheng et al., shows a method of CMP where a SOG layer is coated over the oxide.
U.S. Pat. No. 5,721,173 issued Feb. 24, 1998 to Yano et al., shows another CMP process using a SiN stop layer.
U.S. Pat. No. 5,712,205 issued Jan. 27, 1998 to Park et al., shows a selectively CMP isolation areas on portions of a wafer.
U.S. Pat. No. 5,312,512 issued May 17, 1994 to Allman et al., teaches a method for planarizing which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical mechanical polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by methyl lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on metal lines.
The fabrication of integrated circuits on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic photomasks onto the wafer. The photomasking processing steps opens selected areas to be exposed on the wafer for subsequent processes such as inclusion of impurities, oxidation, or etching.
During the forming of integrated circuit structures, it has become increasingly important to provide structures having multiple metallization layers due to the continuing miniaturization of the circuit elements in the structure. Each of the metal layers is typically separated from another metal layer by an insulation layer, such as an oxide layer. To enhance the quality of an overlying metallization layer, one without discontinuities of other blemishes, it is imperative to provide an underlying surface for the metallization layer that is ideally planar. The process of planarization is necessary and desirable to facilitate masking and etching operations. Planarization of metal interconnect layers improves the yield of devices contained in the device array of a wafer, and the reliability of such devices. Planarization produces a constant thickness across the circuit of a die, minimizes the presence of cavities, and allows metal interconnect lines to be continuous, where they would otherwise be discontinuous over a non-planar surface containing cavities.
To meet the demand for larger scale integration, and more metal and oxide layers in devices and the exacting depth of focus needed for submicron lithography, a new planrization method, known as chemical mechanical polishing (CMP), was developed and is presently used by most major semiconductor manufacturers. CMP planarization of a wafer involves supporting and holding the wafer against a rotating polishing pad wet with a polishing slurry and at the same time applying pressure. Unlike the conventional planarization techniques, CMP provides a substantially improved overall planarization, that is, an improvement of 2 to 3 orders of magnitude over conventional methods. Although CMP planarization is effective, most CMP techniques have difficulties providing trouble free device patterns. Surface microscratches are formed during CMP planarization. These surface anomalies are caused by submicron size silica contained in the polishing slurry.